In the fabrication of conventional very high performance (f.sub.T =15 GHz) bipolar transistors, severe limitations have been put on emitter/base and base/collector junction depths in attempting to produce shallow devices. To fabricate a high-performance transistor, the dopant concentrations in the emitter and base need to be fairly high. On the other hand, high dopant concentrations of the emitter and base tend to diffuse inwardly into the semiconductor layer, increasing the total thickness of the transistor.
Several conventional attempts have been made to fabricate a high-speed bipolar device in very large scale integrated (VLSI) technology. One technique developed in pursuit of this objective is a polysilicon self-aligned device as described by K. Okada in IEEE Journal of Solid State Circuits, Vol. SC-13, No. 5 (October, 1978). In this attempted solution, a self-aligned bipolar device used a local oxide separation method to separate the base region and the (N+) emitter. Due to the size constraints of the oxide, this device does not lend itself to significant size reduction.
In U.S. Pat. No. 4,148,468 issued to M. Vora, a polysilicon-aligned device was disclosed that deposited the (N+) polysilicon initially and then grew a thin spacer oxide, after which a (p+) material was deposited. According to the fabrication of this device, the oxidation was performed at 1000.degree. C., thereby making it difficult to keep the base profile shallow.
These and other conventional approaches have all had their drawbacks in attempting to fabricate a very high performance bipolar device in a VLSI circuit. Accordingly, a need has arisen for a process for fabricating a very high performance bipolar device with shallow emitter/base and base/collector junctions.